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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-21353-1E
ASSP
Dual Serial Input PLL Frequency Synthesizer
MB15F02L
s DESCRIPTION
The Fujitsu MB15F02L is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1.2 GHz and a 250 MHz prescalers. A 64/65 or a 128/129 for the 1.2 GHz prescaler, and a 16/17 or a 32/33 for 250 MHz prescaler can be selected that enables pulse swallow operation. The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 4.0 mA typ. at a supply voltage of 3.0 V. Furthermore, a super charger circuit is included to provide a fast tuning as well as low noise performance. As a result of this, MB15F02L is ideally suitable for digital mobile communications, such as GSM (Global System for Mobile Communications).
s FEATURES
* * * * * * * High frequency operation RF synthesizer: 1.2 GHz max. / IF synthesizer: 250 MHz max. Low power supply voltage: VCC = 2.7 to 3.6 V Very Low power supply current : ICC = 4.0 mA typ. (VCC = 3 V) Power saving function : Supply current at power saving mode Typ.0.1 A (VCC = 3 V), Max.10 A (IPS1 = IPS2) Dual modulus prescaler : 1.2 GHz prescaler (64/65,128/129) , 250 MHz prescaler (16/17,32/33) Serial input 14-bit programmable reference divider: R = 5 to 16,383 Serial input 18-bit programmable divider consisting of: - Binary 7-bit swallow counter: 0 to 127 - Binary 11-bit programmable counter: 5 to 2,047 * On-chip high performance charge pump circuit and phase comparator, achieving high-speed lock-up and low phase noise * On-chip phase control for phase comparator * Wide operating temperature: Ta = -40 to 85C
s PACKAGES
16-pin, Plastic SSOP 16-pin, Plastic BCC
(FPT-16P-M05)
(LCC-16P-M03)
1
MB15F02L
s PIN ASSIGNMENTS
SSOP-16 pin
GNDRF OSCin GNDIF finIF VccIF LD/fout PSIF DoIF
1 2 3 4
16 15 14
Clock Data LE finRF VccRF XfinRF PSRF DoRF
TOP 13 VIEW 5 12 6 7 8 11 10 9
(FPT-16P-M05)
BCC-16 pin GNDRF Clock
OSCin GNDIF finIF VCCIF LD/fout PSIF 1 2 3 4 5 6 7 8 16 15 14 13 12 Date LE finRF VCCRF XfinRF PSRF
Top view
11 10 9
DoIF DoRF (LCC-16P-M03)
2
MB15F02L
s PIN DESCRIPTIONS
Pin no. SSOP 1 2 3 4 5 6 BCC 16 1 2 3 4 5 Pin name GNDRF OSCin GNDIF finIF VCCIF LD/fout I/O - I - I - O Ground for RF-PLL section. The programmable reference divider input. TCXO should be connected with a AC coupling capacitor. Ground for the IF-PLL section. Prescaler input pin for the IF-PLL. The connection with VCO should be AC coupling. Power supply voltage input pin for the IF-PLL section. Lock detect signal output (LD) / phase comparator monitoring output (fout) The output signal is selected by a LDS bit in a serial data. LDS bit = "H" ; outputs fout signal LDS bit = "L" ; outputs LD signal Power saving mode control for the IF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSIF = "H" ; Normal mode PSIF = "L" ; Power saving mode Charge pump output for the IF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Charge pump output for the RF-PLL section. Phase characteristics of the phase detector can be reversed by FC-bit. Power saving mode control for the RF-PLL section. This pin must be set at "L" Power-ON. (Open is prohibited.) PSRF = "H" ; Normal mode PSRF = "L" ; Power saving mode Prescaler complimentary input for the RF-PLL section. This pin should be grounded via a capacitor. Power supply voltage input pin for the RF-PLL section, the shift register and the oscillator input buffer. When power is OFF, latched data of RF-PLL is cancelled. Prescaler input pin for the RF-PLL. The connection with VCO should be AC coupling. Load enable signal input (with the schmitt trigger circuit.) When LE is "H", data in the shift register is transferred to the corresponding latch according to the control bit in a serial data. Serial data input (with the schmitt trigger circuit.) A data is transferred to the corresponding latch (IF-ref counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according to the control bit in a serial data. Clock input for the 23-bit shift register (with the schmitt trigger circuit.) One bit data is shifted into the shift register on a rising edge of the clock. Descriptions
7
6
PSIF
I
8 9
7 8
DOIF DORF
O O
10
9
PSRF
I
11 12 13 14
10 11 12 13
XfinRF VCCRF finRF LE
I - I I
15
14
Data
I
16
15
Clock
I
3
MB15F02L
s BLOCK DIAGRAM
VCCIF 5 3-bit latch
LDS SWIF FCIF
GNDIF 3
7 PSIF
Intermittent mode control (IF-PLL) Prescaler (IF-PLL) 16/17,32/33
7-bit latch
11-bit latch Phase comp.
(IF-PLL)
fpIF Binary 11-bit Binary 7-bit swallow counter programmable counter(IF-PLL) (IF-PLL)
Charge Super pump (IF-PLL) charger
8 DoIF
finIF 4
2-bit latch T1 T2
14-bit latch
Binary 14-bit pro- frIF grammable ref. counter(IF-PLL)
Lock Det.
(IF-PLL)
LDIF
2
OSCin
AND OR frRF T1 T2
Binary 14-bit programmable ref. counter(RF-PLL)
LDRF
Selector LD frIF frRF fpIF fpRF
6 LD/fout
2-bit latch finRF 13
11 XfinRF
14-bit latch
Prescaler
(RF-PLL)
Lock Det.
64/65, 128/129 LDS SWRF FCRF
Intermittent mode control
(RF-PLL)
Binary 11-bit Binary 7-bit swallow counter programmable counter(RF-PLL) (RF-PLL)
Phase comp.
PSRF10
fpRF
(RF-PLL)
Charge Super pump charger (RF-PLL)
9 DoRF
3-bit latch
7-bit latch
11-bit latch
LE14
Schmitt circuit
Schmitt circuit Schmitt circuit
Latch selector
Data15
Clock16
CC NN 12
23-bit shift register
12 1
VCCRF
GNDRF
Note : SSOP-16 pin
4
MB15F02L
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Power supply voltage Input voltage Output voltage Output current Storage temperature Symbol VCC VI VO IO Ido TSTG Rating Min. -0.5 -0.5 -0.5 -10 -25 -55 Max. +4.0 VCC +0.5 VCC +0.5 +10 +25 +125 Unit V V V mA mA C Except Do output Do output Remark
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage Operating temperature Symbol VCC VI Ta Value Min. 2.7 GND -40 Typ. 3.0 - - Max. 3.6 VCC +85 Unit V V C Remark
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. Handling Precautions * This device should be transported and stored in anti-static containers. * This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats. * Always turn the power supply off before inserting or removing the device from its socket. * Protect leads with a conductive sheet when handling or transporting PC boards with devices.
5
MB15F02L
s ELECTRICAL CHARACTERISTICS
(VCC = 2.7 to 3.6 V, Ta = -40 to +85C) Parameter Symbol ICCIF*1 Power supply current ICCRF*2 IpsIF Power saving current finIF*4 finRF*4 OSCin finIF finRF OSCin Data, Clock, LE PSIF, PSRF Data, Clock, LE, PSIF, PSRF OSCin LD/fout Output voltage DoIF, DoRF DoIF, DoRF LD/fout Output current DoIF, DoRF
IpsRF
Condition
Min.
Value Typ. 1.5 2.5 0.1*3 0.1*3 - - - - - - - - - -
Max. -
Unit
Operating frequency
Input sensitivity
finIF finRF fOSC VfinIF VfinRF VOSC VIH VIL VIH VIL IIH*5 IIL*5 IIH IIL*5 VOH
VOL
finIF = 250 MHz, - fosc = 12 MHz finRF = 1200 MHz, - fosc = 12 MHz VCCIF current at PSIF = "L" - VCCRF current at PSIF/RF = - "L" IF-PLL 50 RF-PLL 100 - 3 IF-PLL, 50 termination -10 RF-PLL, 50 termination -10 - 0.5 VCC x 0.7 + 0.4 Schmitt trigger input Schmitt trigger input - - - - - - VCC = 3.0 V, IOH = -1.0 mA VCC = 3.0 V, IOL = 1.0 mA VCC = 3.0 V, IDOH = -1.0 mA VCC = 3.0 V, IDOL = 1.0 mA VCC = 3.0 V, VOFF = GND to VCC VCC = 3.0 V VCC = 3.0 V VCC = 3.0 V, VDOH = 2.0 V, Ta = 25C VCC = 3.0 V, VDOL = 1.0 V, Ta = 25C - VCC x 0.7 - -1.0 -1.0 0 -100 VCC - 0.4 - VCC - 0.4 - - -1.0 - -11 8
mA - 10 10 250 1200 40 +2 +2 VCC -
VCC x 0.3 - 0.4
A
MHz dBm dBm Vp-p V V
Input voltage
- VCC x 0.3 +1.0 +1.0 +100 0 - 0.4 - 0.4 3.0 - 1.0 -6
Input current
- - - - - - - - - - - -
A
A V V nA mA
VDOH VDOL IOFF IOH*5 IOL IDOH*5 IDOL
High impedance cutoff current
mA 15
*1: Conditions ; VCCIF = 3 V, Ta = 25C, in locking state. *2: Conditions ; VCCRF = 3 V, Ta = 25C, in locking state. *3: fosc = 12.8 MHz , VCC = 3.0 V, Ta = 25C *4: AC coupling with a 1000 pF capacitor connected. *5: The symbol "-" (minus) means direction of current flow.
6
MB15F02L
s FUNCTIONAL DESCRIPTIONS 1. Pulse Swallow Function
The divide ratio can be calculated using the following equation: fVCO = {(M x N) + A} x fOSC / R (A < N) fVCO: M: N: A: fOSC: R: Output frequency of external voltage controlled oscillator (VCO) Preset divide ratio of dual modulus prescaler (16 or 32 for IF-PLL, 64 or 128 for RF-PLL) Preset divide ratio of binary 11-bit programmable counter (5 to 2,047) Preset divide ratio of binary 7-bit swallow counter (0 A 127) Reference oscillation frequency Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
2. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sections, programmable reference dividers of IF/RF PLL sections are controlled individually. Serial data of binary data is entered through Data pin. On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit CN1 L H L H CN2 L L H H Destination of serial data The programmable reference counter for the IF-PLL. The programmable reference counter for the RF-PLL. The programmable counter and the swallow counter for the IF-PLL The programmable counter and the swallow counter for the RF-PLL
(1) Shift Register Configuration
* Programmable Reference Counter
LSB 1 C N 1 2 C N 2 3 T 1 4 T 2 5 R 1 6 R 2 7 R 3 8 R 4 Data Flow 9 R 5 10 R 6 11 R 7 12 R 8 13 R 9 14 R 10 15 R 11 16 R 12 17 R 13 18 R 14 MSB
19 X
20 X
21 X
22 X
23 X
CNT1, 2 : Control bit R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383) T1, 2 : Test purpose bit X : Dummy bits(Set "0" or "1") Note: Data input with MSB first.
[Table. 1] [Table. 2] [Table.3]
7
MB15F02L
* Programmable Counter
LSB Data Flow MSB
1 C N 1
2 C N 2
3 L D S
4
5
6 A 1
7 A 2
8 A 3
9 A 4
10 A 5
11 A 6
12 A 7
13 N 1
14 N 2
15 N 3
16 N 4
17 N 5
18 N 6
19 N 7
20 N 8
21 N 9
22 N 10
23 N 11
S F W C IF/ IF/ RF RF
: Control bit : Divide ratio setting bits for the programmable counter (5 to 2,047) : Divide ratio setting bits for the swallow counter (0 to 127) : Divide ratio setting bit for the prescaler (16/17 or 32/33 for the IF-PLL, 64/65 or 128/129 for the RF-PLL) FC IF/RF : Phase control bit for the phase detector LDS : LD/fout signal select bit Note: Data input with MSB first.
CNT1, 2 N1 to N11 A1 to A7 SW IF/RF
[Table. 1] [Table. 4] [Table. 5] [Table. 6] [Table. 7] [Table. 8]
(2) Data Setting
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide ratio (R) 5 6 16383 R 14 0 0 1 R 13 0 0 1 R 12 0 0 1 R 11 0 0 1 R 10 0 0 1 R 9 0 0 1 R 8 0 0 1 R 7 0 0 1 R 6 0 0 1 R 5 0 0 1 R 4 0 0 1 R 3 1 1 1 R 2 0 1 1 R 1 1 0 1
Note: Divide ratio less than 5 is prohibited.
Table3. Test Purpose Bit Setting
T 1 L H L H T 2 L L H H LD/fout pin state Outputs frIF. Outputs frRF. Outputs fpIF. Outputs fpRF.
8
MB15F02L
Table4. Binary 11-bit Programmable Counter Data Setting
Divide ratio (N) 5 6 2047 N 11 0 0 1 N 10 0 0 1 N 9 0 0 1 N 8 0 0 1 N 7 0 0 1 N 6 0 0 1 N 5 0 0 1 N 4 0 0 1 N 3 1 1 1 N 2 0 1 1 N 1 1 0 1
Note: Divide ratio less than 5 is prohibited.
Table5. Binary 7-bit Swallow Counter Data Setting
Divide ratio (A) 0 1 127 A 7 0 0 1 A 6 0 0 1 A 5 0 0 1 A 4 0 0 1 A 3 0 0 1 A 2 0 0 1 A 1 0 1 1
Note: Divide ratio (A) range = 0 to 127
Table6. Prescaler Data Setting
SW = "H" Prescaler divide ratio IF-PLL RF-PLL 16/17 64/65 SW = "L" 32/33 128/129
Table7. Phase Comparator Phase Switching Data Setting
FCIF,RF = H fr > fp fr = fp fr < fp VCO polarity H Z L (1) FCIF,RF = L
(1)
DoIF,RF L Z H (2)
VCO output frequency
Note: * Z = High-impedance * Depending upon the VCO and LPF polarity, FC bit should be set.
(2) VCO output voltage
Table8. LD/fout Output Select Data Setting
LDS H L LD/fout output signal fout (frIF/RF, fpIF/RF) signals LD signal
9
MB15F02L
3. Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PSIF(RF) pin to Low, IF-PLL (RF-PLL) enters into power saving mode resultant current consumption can be limited to 10 A (typ.). Setting PS pin to High, power saving mode is released so that the device works normally. In addition, the intermittent operation control circuit is included which helps smooth start up from stand by mode. In general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and comparison frequency (fp) and may in the worst case take longer time for lock up of the loop. To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up. Thus keeping the loop locked. PS pin must be set "L" at Power-ON. Allow 1 s after frequency stabilization on power-up for exiting the power saving mode (PS: L to H) Serial data can be entered during the power saving mode. During the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 A per one PLL section. At that time, the Do and LD become the same state as when a loop is locking. That is, the Do becomes high impedance. A VCO control voltage is naturally kept at the locking voltage which defined by a LPF's time constant. As a result of this, VCO's frequency is kept at the locking frequency. PSIF L H L H PSRF L L H H IF-PLL counters OFF ON OFF ON RF-PLL counters OFF OFF ON ON OSC input buffer OFF ON ON ON
ON
VCC Clock Data LE PS (1) (2) (3)
(1) PS = L (power saving mode) at Power-ON (2)Set serial data after power supply remains stable. (3)Release saving mode(PS : L H) after setting serial data.
10
MB15F02L
4. Serial Data Input Timing
1st. data 2nd. data
Control bit
Invalid data
Data
MSB
LSB
Clock
t1 t7 t2 t5 t4
LE
t3 t6
On rising edge of the clock, one bit of the data is transferred into the shift register.
Parameter
t1 t2 t3 t4
Min.
20 20 30 20
Typ.
- - - -
Max.
- - - -
Unit
ns ns ns ns
Parameter
t5 t6 t7
Min.
30 100 100
Typ.
- - -
Max.
- - -
Unit
ns ns ns
11
MB15F02L
s PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU LD (FC bit = High) H DoIF/RF Z
tWL
L
(FC bit = Low) DoIF/RF Z
LD Output Logic Table
IF-PLL section
Locking state / Power saving state Locking state / Power saving state Unlocking state Unlocking state
RF-PLL section
Locking state / Power saving state Unlocking state Locking state / Power saving state Unlocking state
LD output
H L L L
Note: * Phase error detection range = -2 to +2 * Pulses on DoIF/RF signals are output to prevent dead zone. * LD output becomes low when phase error is tWU or more. * LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more. * tWU and tWL depend on OSCin input frequency as follows. tWU 4/fosc: i.e. tWU 312.5 ns when foscin = 12.8 MHz tWL 8/fosc: i.e. tWL 625.0 ns when foscin = 12.8 MHz
12
MB15F02L
s TEST CIRCUIT (fin, OSCIN Input Sensitivity Test)
fout Oscilloscope VCCIF 0.1 F 1000 pF S.G 50 1000 pF S.G 50 8 7 6 5 4 3 2 1 GND
MB15F02L
9 S.G 1000 pF 50
10
11
12
13
14
15
16
Controller (divide ratio setting) VCCRF 1000 pF 0.1 F
Note : SSOP-16 pin
13
MB15F02L
s TYPICAL CHARACTERISTICS 1. fin Input Sensitivity
Input sensitivity of fIN (RF) vs. Input frequency 10 5 0 Vfin RF (dBm) -5 -10 -15 -20 -25 -30 -35 -40 0 500 1000 fin RF (MHz) Input sensitivity of fIN (IF) vs. Input frequency 10 5 0 -5 Vfin IF (dBm) -10 -15 -20 -25 -30 -35 -40 0 250 500 fin IF (MHz) 750 1000 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V 1500 2000
,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,,
SPEC
Ta = +25C
V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V
,,,, ,,,, ,,,,
SPEC
Ta = +25C
2. OSCin Input Sensitivity
Input sensitivity of OSCin vs. Input frequency +10
0 Input sensitivity V OSC
-10
,,,,,,,,, ,,,,,,,,, ,,,,,,,,,
SPEC
Ta = +25C
-20
-30 V CC = 2.7 V V CC = 3.0 V V CC = 3.6 V 0 50 Input frequency f OSC 100 (MHz)
-40
14
MB15F02L
3. DORF Output Current
I DOH vs. V DOH
5.000
V CC = 3.0 V Ta = +25C
V DOH (V) 0.0 0.0 I DOH (mA) -25.0
I DOL vs. V DOL 5.000 V CC = 3.0 V Ta = +25C
V DOL (V) .0000 .0000 I DOL (mA)
25.00
15
MB15F02L
4. DOIF Output Current
I DOH vs. V DOH
5.000
V CC = 3.0 V Ta = +25C
V DOH (V) .0000 .0000 I DOH (mA)
-25.00
I DOL vs. V DOL
5.000
V CC = 3.0 V Ta = +25C
V DOL (V) .0000 .0000 I DOL (mA)
25.00
16
MB15F02L
5. fin Input Impedance
fin 1: 309 -640.13 100 MHz 29.773 -186.98 400 MHz 12.648 -83.883 800 MHz
2:
3: fin RF
1
4 : 10.252 -43.703 1.2 GHz
2 4 3
START 100.000 000 MHz STOP 1 200.000 000 MHz
fin 1: 791.22 -907.56 50 MHz 89.189 -378.02 200 MHz 58.797 -304.36 250 MHz
2:
3: fin IF
START 50.000 000 MHz
STOP 500.000 000 MHz
17
MB15F02L
6. OSCIN Input Impedance
OSC IN
1:
7.138 k -23.837 k 3 MHz 257 -6.214 k 10 MHz 154 -2.9594 k 20 MHz 83.88 -1.5472 k 40 MHz
2:
3:
OSC IN
4 1
3
2
4:
START 1.000 000 MHz
STOP 50.000 000 MHz
18
MB15F02L
s REFERENCE INFORMATION (Lock Up Time, Phase Noise, Reference Leakage)
Test Circuit S.G OSCin fin Do LPF f VCO = 810.45 MHz K V = 17 MHz/V fr = 25 kHz f OSC = 14.4 MHz LPF
9.1 k
Spectrum analyzer
6800 pF VCO
2.7 k 0.068 F
1500 pF
PLL reference leakage
RL -5.0 dBm 10 dB/ MKR -74.00 dB 25.0 kHz RL -5.0 dBm
PLL phase noise
10 dB/ MKR -51.83 dB 1.67 kHz
C/N ~ 71.8 dBc/Hz 74.0 dBc
BW ~ 4.17 KHz
CENTER 810.4500 MHz RBW 1.0 kHz VBW 1.0 kHz
SPAN 200.0 kHz SWP 1.00 sec
CENTER 810.45000 MHz RBW 100 Hz VBW 100 Hz
SPAN 20.00 kHz SWP 3.00 sec
PLL lock up time
810.45 MHz826.45 MHz1 kHz 1.32 ms 30.00500 MHz 30.00500 MHz
PLL lock up time
826.45 MHz810.45 MHz 1.64 ms
2.000 kHz/diu
2.00 kHz/diu
29.99500 MHz 0 s 8.0000000 ms
29.99500 MHz 0 s 8.0000000 ms
50.00000 MHz
50.00000 MHz
10.00000 MHz/diu
5.00000 MHz/diu
0 Hz 0 s 8.0000000 ms
25.00000 MHz 0 s 8.0000000 ms
19
MB15F02L
s APPLICATION EXAMPLE
Output VCO 3V From controller 1000 pF 0.1 F 1000 pF LPF
Clock 16
Data 15
LE 14
finRF 13
VCCRF 12
XfinRF 11
PSRF 10
DoRF 9
MB15F02L
1
2
3 GNDIF
4 finIF
5 VCCIF
6 LD/fout
7 PSIF
8 DoIF
GNDRF OSCIN
3V 1000 pF 1000 pF 0.1 F TCXO Lock Det.
Output VCO LPF
Note : SSOP-16 pin
20
MB15F02L
s ORDERING INFORMATION
Part number MB15F02LPFV1 MB15F02LPV Package 16 pin, Plastic SSOP (FPT-16P-M05) 16 pin, Plastic BCC (LCC-16P-M03) Remarks
21
MB15F02L
s PACKAGE DIMENSIONS
16 pins, Plastic SSOP (FPT-16P-M05)
* 5.000.10(.197.004)
*: These dimensions do not include resin protrusion.
1.25 -0.10 +.008 .049 -.004
+0.20
0.10(.004)
INDEX
*4.400.10
(.173.004)
6.400.20 (.252.008)
5.40(.213) NOM
0.650.12 (.0256.0047)
0.22 -0.05 +.004 .009 -.002
+0.10
"A"
0.15 -0.02 +.002 .006 -.001
+0.05
Details of "A" part 0.100.10(.004.004) (STAND OFF)
4.55(.179)REF
0
10
0.500.20 (.020.008)
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in mm (inches).
(Continued)
22
MB15F02L
(Continued)
16 pins, Plastic BCC (LCC-16P-M03)
4.550.10 (.179.004) 0.80(.032)MAX
9
3.40(.134)TYP
9
14
(Mounting height)
0.65(.026)TYP
14
0.400.10 (.016.004) 4.200.10 (.165.004) 45 3.25(.128) TYP "A" "B" 1.55(.061)TYP
0.80(.032) TYP
1
E-MARK
6
0.40(.016) 0.0850.040 (.003.002) (STAND OFF)
6
0.3250.10 (.013.004)
1.725(.068) TYP
1
Details of "A" part 0.750.10 (.030.004) 0.05(.002)
Details of "B" part 0.600.10 (.024.004)
0.400.10 (.016.004)
0.600.10 (.024.004)
C
1996 FUJITSU LIMITED C16014S-1C-1
Dimensions in mm (inches).
23
MB15F02L
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9706 (c) FUJITSU LIMITED Printed in Japan
24

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